Digital signal processing systems and more especially large digital signal processing systems may be divided into several electronic subsystems. The electronic subsystems may be implemented or realized on different circuits boards. They may comprise several field programmable gate arrays (FPGA). The electronic subsystems may be remote from each other. Data are transmitted between the electronic subsystems for example by cables or interconnect boards. Other interconnection means for data transmission are also possible, for example radio interfaces or optical transmission lines.
A digital signal processing system or more generally an electronic system may support multiple clock domains. A clock domain consists of all sequential elements for example registers driven by that clock and all logic elements processing directly or indirectly signals from registers of that clock domain. Each clock domain may span over multiple electronic subsystems of the digital signal processing system. An electronic subsystem may include one unique clock domain or several clock domains.
FIG. 1 shows an exemplary electronic system 10 which is a digital signal processing system comprising a first electronic subsystem 12, a second electronic subsystem 14, and a third electronic subsystem 16. Each subsystem 12, 14 and 16 may be implemented on a different circuit board. The first subsystem 12 comprises internal logic 18, second subsystem 14 comprises internal logic 20 and third subsystem 16 comprises internal logic 22. The internal logics 18, 20 and 22 are adapted to produce a desired function of the electronic system 10 and comprise for example FPGAs.
The first subsystem 12 comprises a clock generator 24 and four flip flops 26a, 26b, 26c and 26d which are coupled to clock generator 24 via a clock line 28. Flip flops 26a, 26b, 26c and 26d are further coupled to internal logic 18. The first subsystem 12 further comprises two buffers 30a, 30b. Second and third subsystems 14 and 16 also comprise flip flops and a buffer each.
A first buffer 30a is coupled via a clock transmission line 32 to the buffer of the second subsystem 14 which is coupled with an output to a clock line 34. The buffer 30b is coupled via a clock transmission line 36 to the buffer of the third subsystem 16 which is coupled to a clock line 38.
Flip flop 26a is coupled with an output via a data transmission line 40 to second subsystem 14, and flip flop 26b is coupled with an output via a data transmission line 42 to second subsystem 14. Flip flop 26c is coupled with an output via a data transmission line 44 to third subsystem 16, and flip flop 42 is coupled with an output via a data transmission line 46 to third subsystem 16.
Data transmission lines 48 and 50 couple the second and the third subsystem with each other to exchange data between the second subsystem 14 and the third subsystem 16.
In operation, clock generator 24 generates a clock signal which is distributed throughout the first subsystem 12 via clock line 28. The clock signal is transmitted to second subsystem 14 via buffer 30a and clock line 32 and distributed throughout second subsystem 14 via clock line 34. The clock signal is further transmitted to third subsystem 16 via buffer 30b and clock line 36 and distributed throughout third subsystem 16 via clock line 38.
First subsystem 12 sends data from the internal logic 18 via flip flop 26a, data transmission line 40 and a flip flop in second subsystem 14 to the internal logic 20 of second subsystem 14. First subsystem 12 receives data from the internal logic 20 via data transmission line 42. Similarly, first subsystem 12 exchanges data with third subsystem 16 via flip flop 26c, data transmission line 44, data transmission line 46 and flip flop 26d. Second and third subsystems 14 and 16 exchange data via data transmission lines 48 and 50 and corresponding flip flops. All flip flops in all subsystems 12, 14 and 16 are clocked by the clock signal generated by clock generator 24. Internal logics 18, 20 and 22 are also clocked by the same clock signal.
The prior art digital signal processing system 10 as shown in FIG. 1 thus distributes the clock signal generated in subsystem 12 over the whole system 10. Three problems arise with such a clock distributing system.
Firstly, data signals travelling from the first subsystem 12 on data transmission line 40 to the second subsystem 14 race against the clock signal travelling on the clock transmission line 32 in the same direction, i.e. from the first subsystem 12 to the second subsystem 14. If the data transmission is slower, data will arrive after the clock edge. It can then be processed in the receiving subsystem 14 and the result is stored in the target register at the succeeding clock edge. This is what the digital circuit designer intends. However, the data signal may also win the race against the clock signal. In this case it may be stored in the target register virtually at the same clock edge as it has been generated. This is a design error and may lead to a faulty function of the digital signal processing system 10.
Secondly, due to the travel delay of the clock signal, registers in the second subsystem 14 and the third subsystem 16 operate later than registers in the first subsystem 12. Signals which are sent from registers in the second subsystem 14, i.e. comprised in the internal logic 20, to the first subsystem 12, have about the same travel delay. As a result, registers in the first subsystem 12 see twice the delay, i.e. the delay of the clock travelling from the first subsystem 12 to the second subsystem 14 and the delay of the data travelling from the second subsystem 14 to the first subsystem 12. This significantly reduces the possible clock frequency.
Thirdly, for data signals travelling on the data transmission lines 48 and 50 between the second subsystem 14 and the third subsystem 16, there is no safe timing assumption possible. Faulty processing may occur.
As a result, in the prior art each signal must be treated individually with care during the design process which enormously increases the design effort.
To avoid the before mentioned problems, modern digital signal processing systems use clock synthesis techniques to generate the same clock on all subsystems. The challenge of this approach is to ensure that all individually generated clocks have the same frequency and the same phase.
It is therefore an object of the present invention to provide a method of distributing a clock signal in a first electronic subsystem and a second electronic subsystem ascertaining that a same clock signal having the same frequency and the same phase is distributed all over the system.
It is further an object of the invention to provide a clock distributing system and an electronic system comprising a clock distributing system.